1. Field of the Invention
This invention relates to a method and apparatus for pretreating an electronic component manufacturing frame such as a leadframe. More particularly, the present invention relates to a method and apparatus for peening surfaces of a leadframe before using it for manufacturing electronic components.
2. Description of the Prior Art
As is well known, electronic components or semiconductor devices such as ICs or LSIs are typically made by using a specially designed manufacturing frame called "leadframe". Due to a recent tendency of highly integrating electronic components, the leadframe is also made to have a highly sophisticated pattern.
FIGS. 15 through 18 show an example of highly sophisticated leadframe. Specifically, the leadframe generally represented by reference sign F includes a plurality of chip bonding islands (d) (only one shown) each surrounded by a rectangularly arranged group of dam bars (a). Each of the islands (d) is connected to the leadframe via support bars (h).
The leadframe F further includes a group of outer leads (b) extending outwardly from each dam bar (a), and a group of inner leads (c) extending inwardly from the dam bar toward a corresponding island (d). Initially, the group of inner leads (c) have wire bonding ends connected to each other by a tie bar (e), as shown in FIG. 16.
The leadframe F may have a small thickness of 0.2 mm for example. Further, due to the high degree of integration, the outer leads (b) in each group may be densely arranged at a small pitch of 0.5 mm for example. Obviously, the pitch between the inner leads (c) in the same group is substantially equal to that between the outer leads (b) but reduces progressively toward the chip bonding island (d) (see FIGS. 15, 16 and 18).
In manufacture of electronic components, a semiconductor chip (not shown) is first bonded to each chip bonding island (d) of the leadframe F. Then, an electrically insulating adhesive tape (f) is applied to the inner leads (c) near each tie bar (e), and the tie bar (e) is cut off the inner leads (c) (see FIG. 18). Then, the chip is electrically connected to the inner leads (c) via metal wires (not shown). Then, a resin package is formed for a portion of the leadframe F (including the unillustrated chip) surround by each rectangularly group of dam bars (a), and portions of the dam bars (a) between the respective outer leads (b) are removed for making the respective outer leads (b) (and the inner leads as well) electrically independent from each other. Finally, the outer leads (b) and the support bars (h) are cut off the leadframe F, and the outer leads (b) are suitably bent.
The leadframe F may be prepared by etching a thin metal sheet for example. However, the etching method has been found very time-taking and costly.
Alternatively, the leadframe F may be prepared by punching a thin metal sheet. However, the punched leadframe has been found to be disadvantageous in the following respects.
First, the punched leadframe F is made to have localized internal stresses which result from the punching operation. Such stresses cause the leadframe F to have a tendency of warping, thereby failing to provide a high degree of flatness as required for providing a good product quality.
Secondly, the localized internal stresses of the leadframe also cause the inner leads (c) to deform at the time of severing from the tie bars (e). Obviously, such a deformation of the inner leads (c) results in improper wire bonding or shorting contact between the inner leads (c), consequently reducing the production yield of the electronic components (namely, reducing the production cost). While it is possible to restrain the deformation of the inner leads (c) by the electrically insulating resin tape (f) (FIG. 16) to a certain extent, the tape will not remove the deforming tendency of the inner leads (c). The use itself of the tape (f) causes a production cost increase.
In the third place, the punching operation will inevitably results in formation of burrs (g) (see FIG. 17) at the various edges of the leadframe F (including the edges of the respective leads). Obviously, due to the presence of the burrs, the resin package (not shown) subsequently formed will have a tendency of allowing moisture entry at the burrs, thereby causing a quality deterioration (e.g. a circuit fault). Further, the presence of the burrs (g) (FIG. 17) hinders a solder plating operation which is required for improve electrical connection between the respective leads (b, c) and their associated elements.